Required Sensor Power – Part 1

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New functionality was recently added to Signal Chain Explorer that computes the minimum sensor power required to achieve a desired SNR (or ENOB) for a particular signal chain. This feature was originally experimental, but it didn’t take us long to decide to include it as an official part of the product. It brings valuable insight into the limits of any signal chain design, particularly when higher resolution is sought. With this feature you’ll easily see just how impractical it might be to seek high resolution — unless you take care in keeping noise down.

In Part 1 of this Short and Sweet article, we derive the formulas used to compute the required minimum sensor power, and along with it, the required input voltage and input current. In Part 2, we’ll see these formulas put to use in Signal Chain Explorer.

From SNR to Required Sensor Power

Here is the high-level diagram we’ll be working with in this article:

signal-power-high-level

Suppose we have an input signal \(\displaystyle {{S}_{{vi}}}\) which is processed through a signal chain having a gain of \(\displaystyle G(s)\), an input impedance of \(\displaystyle InZ(s)\), and a noise voltage referred to output \(\displaystyle {{N}_{{vo}}}\). In the signal chain, we model the sensor input as an ideal voltage source, and then include a model for the gain, impedance, and noise of the sensor itself, followed by any signal conditioning circuitry, followed by a model of the gain, impedance and noise of any A/D converter included in the signal chain. We tack on a “ideal” set of comparators for the A/D, and it’s right at the input of these comparators that we measure the output voltage and the noise referred to output.

The goal is to find what minimum input voltage gives us a desired SNR (and by inference, a desired ENOB). From this minimum input voltage, if we also calculate the input impedance \(\displaystyle InZ(s)\) of the entire signal chain, the minimum required power delivered by the sensor can be found.

NOTE: By SNR, we really mean SINAD — where we total all sources of noise and distortion that can be root-sum-squared into a single RMS voltage. Even so, we’ll keep using the term SNR in this article anyway, but please think of it in the general sense.

One thing to realize from our high-level diagram: We can compute SNR two ways, (1) by referring the signal chain noise to input and computing \(\displaystyle SNR={{{{S}_{{vi}}}}}/{{{{N}_{{vi}}}}}\;\), or (2) by using the noise referred to output and computing \(\displaystyle SNR={{{{S}_{{vo}}}}}/{{{{N}_{{vo}}}}}\;\). As the diagram shows, these two forms are equivalent.

For convenience of calculation, we choose the first method, and note that

\(\displaystyle {{N}_{{vi}}}={{{{N}_{{vo}}}}}/{{\left| {G(s)} \right|}}\;\),

where \(\displaystyle {\left| {G(s)} \right|}\)

is the magnitude of the signal chain gain. Thus,

\(\displaystyle SNR=\frac{{{{S}_{{vi}}}}}{{{{N}_{{vi}}}}}=\frac{{{{S}_{{vi}}}}}{{{{{{N}_{{vo}}}}}/{{\left| {G(s)} \right|}}\;}}=\frac{{{{S}_{{vi}}}\times \left| {G(s)} \right|}}{{{{N}_{{vo}}}}}\)

Solving for \(\displaystyle {{S}_{{vi}}}\):

\(\displaystyle {{S}_{{vi}}}=\frac{{SNR\times {{N}_{{vo}}}}}{{\left| {G(s)} \right|}}\)

This equation tells us that if we have a desired SNR, and know the signal chain noise referred to output, and know the system’s gain, we can compute the required signal input voltage that will give us that SNR.

NOTE: You might wonder why we are taking the magnitude of the gain in the equations above. Realize that all voltages referenced are real-valued RMS voltages. Also realize that SNR is a unit-less measure, and since \(\displaystyle {{S}_{{vi}}}\) and \(\displaystyle {{N}_{{vi}}}\) are real-valued, then so must be the gain term. Since the signal chain gain is in general complex, we take its magnitude to make it real-valued.

As an aside, we’ll next show the formula for the required output voltage. It’s quite easy if you use the noise voltage referred to output:

\(\displaystyle {{S}_{{vo}}}=SNR\times {{N}_{{vo}}}\)

Okay, then. We are on the road to computing required power. But there’s one more piece to the puzzle. Suppose our signal chain has an input impedance of \(\displaystyle InZ(s)\). This is the load on our idealized sensor voltage source:

signal-chain-input-impedance

With this in place, we can finally talk about the required power delivered by the idealized sensor, using the power version of Ohm’s law:

\(\displaystyle {{S}_{{pi}}}(s)=\frac{{{{S}_{{vi}}}^{2}}}{{InZ(s)}}=\frac{{{{{(SNR\times {{N}_{{vo}}})}}^{2}}}}{{{{{\left| {G(s)} \right|}}^{2}}}}\times \frac{1}{{InZ(s)}}=\frac{{SN{{R}^{2}}\times {{N}_{{vo}}}^{2}}}{{{{{\left| {G(s)} \right|}}^{2}}\times InZ(s)}}\)

Power factor

We’ve denoted the signal power to be frequency dependent (using the Laplacian frequency term \(\displaystyle {s}\). Using \(\displaystyle s\to j\omega \) we can also write this as:

\(\displaystyle {{S}_{{pi}}}(j\omega )=\frac{{SN{{R}^{2}}\times {{N}_{{vo}}}^{2}}}{{{{{\left| {G(j\omega )} \right|}}^{2}}\times InZ(j\omega )}}\)

Since the sensor power is a complex variable, we can define the following four power terms:

  • \(\displaystyle \text{Apparent}\,\text{power}=\left| {{{S}_{{pi}}}(j\omega )} \right|\)
  • \(\displaystyle \text{Real}\,\text{power}={Re}({{S}_{{pi}}}(j\omega ))\)
  • \(\displaystyle \text{Reactive}\,\text{power}={Im}({{S}_{{pi}}}(j\omega ))\)
  • \(\displaystyle \text{Power facto}{{\text{r}}^{*}}=Sgn(Im(InZ(j\omega )))\times \frac{{\text{Real power}}}{{\text{Apparent power}}}\)

* The power factor ranges from 0 to 1, where 1 means all real (dissipative) power. But as a convention (unique to Robust Circuit Design), we also attach a sign to the power factor that helps describe the nature of the reactive part of power — if it exists. If the sensor load is capacitive, (meaning the imaginary part of the load is negative), we make the power factor negative. If the sensor load is inductive (meaning the real part of the load is positive), we make the power factor positive. We stress that this convention is ours alone here at Robust Circuit Design. Don’t be confused.

What if you have a current-source-based sensor?

The formulas above were derived for a voltage-source-based sensor. If your sensor has a current source as its basis, then the minimum current needed can be computed by using the required output voltage and the gain. We showed the formula earlier for required output voltage — it’s an easy derivation from the SNR formula. But the gain term is different. The gain is not a voltage-gain, but rather a trans-impedance gain — that is, going from input current to output voltage. So we end up with:

\(\displaystyle {{I}_{{in}}}=\frac{{{{S}_{{vo}}}}}{{\left| {G(s)} \right|}}=\frac{{SNR\times {{N}_{{vo}}}}}{{\left| {G(s)} \right|}}\quad \text{where }G(s)\,\text{is trans-impedance gain}\)

What if you have a charge-source-based sensor?

If your sensor is based on a charge input signal, then you can use the same method that was used for a current-source-based sensor, except now the trans-impedance gain should convert from input charge to output voltage:

\(\displaystyle {{Q}_{{in}}}=\frac{{{{S}_{{vo}}}}}{{\left| {G(s)} \right|}}=\frac{{SNR\times {{N}_{{vo}}}}}{{\left| {G(s)} \right|}}\quad \text{where }G(s)\,\text{is trans-impedance gain}\)

A Simple Example

To see these formulas come to life, let’s look at a simple example involving a signal chain that has just two stages: (1) A sensor stage consisting of an ideal voltage source, and (2) a low-pass filter stage.

simple-example

To compute required sensor power, we need to know the gain, input impedance, and noise voltage of the low pass filter. We’ve covered these in other Short and Sweet articles, here, here, and here. The relevant formulas are shown below in \(\displaystyle j\omega \) form:

\(\displaystyle G(s)=\frac{1}{{1+RCs}}\quad \Rightarrow \quad G(j\omega )=\frac{1}{{1+j\omega RC}}\)

\(\displaystyle InZ(s)=R+\frac{1}{{Cs}}\quad \Rightarrow \quad InZ(j\omega )=R+\frac{1}{{j\omega C}}\)

\(\displaystyle {{N}_{v}}=\sqrt{{{{KT}}/{C}\;}}\)

Suppose we have R=6.25 Ohms, C=1μF. This gives the filter a corner frequency of

\(\displaystyle {{F}_{c}}=\frac{1}{{2\pi RC}}=25.465\,kHz\).

Its effective noise bandwidth, that you saw how to compute here, is

\(\displaystyle ENBW=\frac{\pi }{2}\times 25.465\,kHz=40\,kHz\).

Suppose we’d like to find the SNR in the flat part of the filter’s curve, say at 1 kHz. That will be our frequency of interest (FOI), and from that we can compute \(\displaystyle j\omega \):

\(\displaystyle j\omega =j2\pi f=j2\pi \times 1\times {{10}^{3}}=6.2832\times \ {{10}^{3}}rad/s\)

UPDATE: Earlier versions of this post used an FOI of 10 kHz. We changed to 1 kHz to be further into the flat part of the gain curve.

Plugging all this in we get the following at 1 kHz:

\(\displaystyle \left| {G(j\omega )} \right|=\left| {\frac{1}{{1+j\omega RC}}} \right|=\left| {\frac{1}{{1+j6.2832\times {{{10}}^{3}}\times 6.25\times 1\times {{{10}}^{{-6}}}}}} \right|=0.99923\)

\(\displaystyle InZ(j\omega )=R+\frac{1}{{j\omega C}}=6.25+\frac{1}{{j6.2832\times {{{10}}^{3}}\times {{{10}}^{{-6}}}}}=6.25-159.155j\)

Notice the minus sign in the imaginary part of this impedance. That minus sign implies that the impedance — which is the sensor load, is capacitive in nature. You’ll see this come into play later.

Now, suppose we’d like an SNR equivalent of 24 bits of resolution. You saw in an earlier Short and Sweet article how to compute a signal to noise ratio using ENOB. Here’s the non-dB version of the formula:

\(\displaystyle SNR={{2}^{N}}\sqrt{{{3}/{2}\;}}={{2}^{{24}}}\sqrt{{{3}/{2}\;}}=20,547,809\)

That’s right. To get 24 bits of resolution, you need a signal that is over 20 million times stronger than the noise in the system. Let’s compute the noise voltage now, assuming the temperature is 290 degK:

\(\displaystyle {{N}_{v}}=\sqrt{{{{KT}}/{C}\;}}=\sqrt{{1.38\times {{{10}}^{{-23}}}\times 290/{{{10}}^{{-6}}}}}=63.26\,nV\).

From this, we can compute the signal chain output voltage at 1 kHz as:

\(\displaystyle {{S}_{{vo}}}=SNR\times {{N}_{{vo}}}=20,547,809\times 63.26\times {{10}^{{-9}}}=1.3\ Vrms\)

Now we can compute the required input voltage, and then, using the system’s input impedance, the required signal power, all at 10 kHz:

\(\displaystyle {{S}_{{vi}}}=\frac{{{{S}_{{vo}}}}}{{\left| {G(j\omega )} \right|}}=\frac{{1.3}}{{0.99923}}=1.301\ Vrms\)

\(\displaystyle {{S}_{{pi}}}(j\omega )=\frac{{{{S}_{{vi}}}^{2}}}{{{{{\left| {G(j\omega )} \right|}}^{2}}}}\times \frac{1}{{InZ(j\omega )}}={{1.301}^{2}}\times \frac{1}{{6.25-159.155j}}=0.000417+0.01063j\)

Taking the magnitude of this will give us the apparent power, which comes in at 10.64 mVA. The real and reactive powers come in at 417 uW and 10.63 mVAR, respectively. The sensor power has a large reactive component, so the power factor will be on the small side. It comes in at:

\(\displaystyle \text{Power factor}=Sgn({Im}(InZ(j\omega )))\times \frac{{\text{Real power}}}{{\text{Apparent power}}}=(-)\frac{{0.00042}}{{0.0106}}=-0.0392\)

Per our local conventions, we’ve given the power factor a minus sign to signify that the required power is delivered to a capacitive load.

What does this mean?

We noted earlier that our low-pass filter had a 40 kHz effective noise bandwidth. And we note that to achieve 24-bits of resolution, we need a signal power of at least 10.64 mVA. You’ll be interested to note that this required apparent power is the same no matter what value is used for the resistance (as long as the capacitance is correspondingly changed to keep the filter at 40 kHz effective noise bandwidth, and we stay with a 1 kHz signal.) You’ll see this come to life in Part 2.

We think this is an interesting result. A 40 kHz bandwidth is not too far off from what a simple system to digitize audio might have.  It tells us something general about what it takes to achieve 24 bits of resolution in such an analog to digital signal chain — assuming that you are using a straight forward A/D converter that does not use over-sampling. We mentioned in the previous article on ENOB that the formulas we’re using here assume no over-sampling.

What’s the impact of this result? We’re not sure — but we note that armed with the formulas above, such thought experiments are possible.

Summary

In this article we derived the formulas for computing the required sensor power (and voltage and current) at a given frequency for a desired SNR and a given signal chain. You should note that these formulas are built-in to Signal Chain Explorer. We know of no other tool that computes these numbers for you so easily. In fact, we know of no other tool that even talks about them at all! We think they will be invaluable to you — they give you insights into just what it takes to achieve a high resolution signal. You’ll most likely be surprised when you move to resolutions higher than 16 bits. You’ll see that things can quickly get out of hand — and Signal Chain Explorer will show you just out of hand that can be. You’ll learn to appreciate taking charge and controlling the noise in your system. You’ll see examples of this in Part 2 of this Short and Sweet article.

 

 

 

 

 

 

Understanding Effective Number of Bits

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One of the main figures of merit computed by Signal Chain Explorer is the Effective Number of Bits (ENOB) of your signal chain. In this Short and Sweet article we’ll explain how that number is computed. The ENOB value relates the Signal to Noise Ratio (SNR) of a system in regards to digitized output. For example, if your system outputs 16-bit data words, how many of those bits are actually useful? The useful number of bits is called the effective number of bits, and is less than the ideal because of noise in the system.

Manufacturers of A/D converters (ADCs) use the ENOB number as one measure of the quality of their converters. While the ENOB term is usually associated with ADCs, it can also be used as a measure of an entire signal chain — not just the ADC. You’ll see how that’s done in this article. But first, let’s look at ADCs by themselves, starting with mythical ideal converters that have no errors, noise, or distortion other than that caused by the quantization itself.

Ideal ADC Resolution

There are many sources of errors that can occur in a converter: Thermal noise, harmonic distortion caused by non-linearity, jitter, interference, etc. But we’re going to focus on just one source: the quantization noise. In an ideal ADC, that’s the only noise it has — but note that it will have such noise. There’s no getting around it. It’s inherent in the process of digitization.

NOTE: In this article we’ll be discussing basic Nyquist-sampling ADCs, not the fancy over-sampling ADCs, including ones that purposely inject a small dither voltage into the input. These fancy ADCs can have less quantization noise than what’s discussed here.

Suppose you have an ADC that has a full scale input of FS Vpp and data word size of N bits. The converter does its best to break up that full scale range into equal-sized chunks called quanta. There are \(\displaystyle {{2}^{N}}\) levels possible in a N bit converter, and \(\displaystyle {{2}^{N}}\) quantas.

Mathematically, we write:

\(\displaystyle Numlevels={{2}^{N}}\)

\(\displaystyle Q=\frac{{FS}}{{{{2}^{N}}}}\quad \text{ }\!\!\{\!\!\text{ V }\!\!\}\!\!\text{ }\)

Here’s an example of the mapping in a lowly 2-bit converter with a 5 V full scale. We picked such a low resolution to emphasize the quantization errors that occur. The following figure shows one way that input voltages could get turned into digital output codes in this converter.

quantization-steps-vii

Our 2 bit ADC converter has \(\displaystyle {{2}^{N}}=4\) levels, and each quanta is 1/4= 1.25 V.

NOTE: The mapping we used in the figure is only one of the possible mappings. What mapping works best really depends on the needs of your application.

Quantization Error

We’ve chosen the code mapping so that a code of 00 corresponds to 0.625 V. But that code really represents all voltages in the range 0 <= X < 1.25.  If the input voltage is 0 V, a 00 code will be output, but to the user of the digital data this code represents 0.625 V. So there’s a representation error of -0.625 V. If the input voltage happens to be 0.625 V, then a 00 code is again output, but there’s no error in the representation. After that, the error goes positive as the input voltage goes up. For example, if the input voltage is, say, 1.24 V, then the 00 code is still output, but now with an error of +0.615 V.

A transition occurs right at an input voltage of 1.25 V. Here the code output will change to a 01, which represents a voltage of 1.875 V. Now we have an error between what the input actually was (1.25 V), and what we represent it to be (1.875 V) of -0.625 V. The error is once again negative.

If the input voltage rises to 1.875 V, then the 01 code accurately represents the voltage, so there’s no error.

And so on, and so forth.

Quantization Noise

As we’ve seen, when a continuous voltage is digitized, there’s an error between what the input voltage is, and what the digital code assigned to it implies. The red line in the error plot of our previous figure shows how this error changes as we sweep the voltage range. Note that the error ranges from -Q/2 (-0.625 V) to +Q/2 (+0.625V).

It’s possible to find a statistical measure for this quantization error by using mean-square analysis. Without further ado, the derivation goes something like this:

\(\displaystyle {{Q}_{{noise}}}^{2}=\frac{1}{Q}\int\limits_{{-Q/2}}^{{+Q/2}}{{{{x}^{2}}dx}}=\left. {\frac{1}{Q}\frac{{{{x}^{3}}}}{3}} \right|_{{-Q/2}}^{{+Q/2}}=\frac{{{{{(Q/2)}}^{3}}}}{{3Q}}-\frac{{{{{(-Q/2)}}^{3}}}}{{3Q}}=\frac{{{{Q}^{2}}}}{{{{2}^{3}}3Q}}+\frac{{{{Q}^{2}}}}{{{{2}^{3}}3Q}}\)

\(\displaystyle {{Q}_{{noise}}}^{2}=\frac{{2{{Q}^{2}}}}{{24Q}}=\frac{{{{Q}^{2}}}}{{12}}\)

From this, we can write the formula for the quantization noise as:

\(\displaystyle {{Q}_{{noise}}}=\frac{Q}{{\sqrt{{12}}}}\quad \{Vrms\}\)

As noted in the formula, this is an RMS value — it is after all the root of a mean-square value. This noise is considered to be random, Gaussian white noise. It’s considered to be uncorrelated with the signal, so that’s why it’s considered random. And it’s assumed that any input voltage is equally likely, and thus any error in the range of errors is equally likely. But that’s not always the case — there could be interaction between signal frequencies and the sampling frequencies in the converter. However, in the absence of information to the contrary, treating the noise as being uncorrelated and random is reasonable.

Let’s write the noise in terms of the full scale voltage and the number of bits by plugging in the equation for quanta we gave earlier. We’ll use this form in a bit:

\(\displaystyle Qnoise=\frac{Q}{{\sqrt{{12}}}}=\frac{{FS}}{{\sqrt{{12}}({{2}^{N}})}}=\frac{{FS}}{{\sqrt{{4\times 3}}({{2}^{N}})}}=\frac{{FS}}{{2\sqrt{3}({{2}^{N}})}}\quad \{\text{Vrms }\!\!\}\!\!\text{ }\)

Signal to Noise Ratio of an Ideal ADC

The signal to noise ratio of a system is defined to be the RMS voltage of the signal divided by the RMS voltage of the system’s noise. For an ideal ADC, which has only quantization noise, we can write:

\(\displaystyle SNR=\frac{{Signa{{l}_{{rms}}}}}{{Nois{{e}_{{rms}}}}}=\frac{{F{{S}_{{rms}}}}}{{Qnoise}}\)

Both terms are RMS voltages, making the ratio unit-less. Since FS is really a peak-to-peak voltage, we must convert it into RMS as follows:

\(\displaystyle F{{S}_{{rms}}}=\frac{{FS}}{{2\sqrt{2}}}\)

Using our definitions for FSrms and Qnoise we can derive:

\(\require{cancel} \displaystyle SNR=\frac{{F{{S}_{{rms}}}}}{{Qnoise}}=\frac{{\cancel{{FS}}}}{{\cancel{2}\sqrt{2}}}\times \frac{{\cancel{2}\sqrt{3}({{2}^{N}})}}{{\cancel{{FS}}}}=\frac{{\sqrt{3}({{2}^{N}})}}{{\sqrt{2}}}={{2}^{N}}\sqrt{{{3}/{2}\;}}\)

In dB:

\(\displaystyle SN{{R}_{{dB}}}=20Log10({{2}^{N}}\sqrt{{{3}/{2}\;}})=20Log10({{2}^{N}})+\,20Log10(\sqrt{{{3}/{2}\;}})\)

\(\displaystyle SN{{R}_{{dB}}}=20Log10(2)N+20Log10(\sqrt{{3/2}})\)

\(\displaystyle SN{{R}_{{dB}}}\approx 6.02N+1.76\)

Effective Number of Bits

Next we’ll consider real-world, non-ideal converters. In the real world, the converters have more than just quantization noise. They have thermal noise, clock jitter noise, non-linearities that cause distortion, outside interference, etc. In the absence of information to the contrary, it’s useful to treat all this noise as uncorrelated, random noise. As such, this noise can be root-sum-squared along with quantization noise to produce the overall RMS noise of the converter:

\(\displaystyle {{N}_{{overall}}}=\sqrt{{Qnois{{e}^{2}}+{{N}_{1}}^{2}+{{N}_{2}}^{2}+…+{{N}_{n}}^{2}}}\quad \{Vrms\}\)

If we replace the Qnoise term in the denominator of our SNR with this overall noise, we end up with what’s called the Signal-to-Noise-And-Distortion (SINAD) ratio:

\(\displaystyle SINAD=\frac{{F{{S}_{{rms}}}}}{{{{N}_{{overall}}}}}\)

Now, suppose we take the equation that relates SNR with N bits, and replace the SNR term with SINAD instead. We can solve for N, and this N is then called the Effective Number of Bits (ENOB) of the converter. For example, using the dB version of the SNR equation we can write:

\(\displaystyle \begin{array}{l}SN{{R}_{{dB}}}=20Log10(2)N+20Log10(\sqrt{{3/2}})\quad \quad \quad \quad \{\text{original equation }\!\!\}\!\!\text{ }\\SINA{{D}_{{dB}}}=20Log10(2)ENOB+20Log10(\sqrt{{3/2}})\quad \{\text{SINAD version }\!\!\}\!\!\text{ }\end{array}\)

Solving for ENOB yields:

\(\displaystyle ENOB=\frac{{SINA{{D}_{{dB}}}-20Log10(\sqrt{{3/2}})}}{{20Log10(2)}}\approx \frac{{SINA{{D}_{{dB}}}-1.76}}{{6.02}}\)

For a given real-world ADC having an N-bit output data width, the ENOB of that converter will be less than N because it will have noise above and beyond the quantization noise. A 16-bit ADC, for example, may actually have an ENOB of 14 bits.

How is ENOB found for a particular device? The steps might be something like the following, for which we will not go into detail (and note there are other ways to determine ENOB):

  • A known signal is input to the device under test.
  • The digital output data of the converter is processed through an FFT, and the frequency spectrum is analyzed. A measure of the strength of the signal is found, along with a measure of the noise. In a real world device, this noise is made up not only of quantization noise, but also thermal noise, harmonic distortion, intermodulation distortion, sampling jitter, etc.
  • Given the signal and noise measurements, the Signal-to-Noise-and-Distortion (SINAD) ratio of the device can be computed.
  • The SINAD term can be used to back-calculate the ENOB.

 

The following figure illustrates the determination of the signal and noise relationship:

measuring-snr

Philosophy of finding ENOB for an entire signal chain

It’s useful to step back and look at the big picture about the implications of using the ENOB formula. We are in effect (pun intended) taking a real world ADC and mapping it to a mythical, ideal ADC. Remember that an ideal ADC has only quantization noise. By using the ENOB formula on our real world ADC, we are pretending that the corresponding, mythical, ideal ADC has quantization noise that just happens to equal the total noise of our real-world ADC. That is,

\(\displaystyle \text{Mythical Ideal }{{Q}_{{noise}}}=\text{Total Real Worl}{{\text{d}}_{{noise}}}\)

If we were to use either device, mythical or real, the quality of their digital outputs would be the same, in terms of useful bits.

This method of determining ENOB can also be applied to an entire signal chain that includes an ADC at the end. Think about it: We have a given input signal, we can look at the digital output of the whole chain, measure the corresponding noise, compute the corresponding SINAD, and find the effective number of bits. It’s as though we’ve packaged up that entire signal chain and placed it inside a black box.

black-box-signal-chain-circuitry

As far as anyone on the outside is concerned, that black box serves exactly the same function that an ADC does: It takes an analog input signal and outputs digital values.

It should be noted that an ADC chip itself is more than just a collection of comparators. It’s a complicated affair, involving much circuitry. Why, that circuitry is exactly like a signal chain!

Signal Chain Explorer uses the above philosophy when computing ENOB for you. By reporting the ENOB, it’s telling you what mythical, ideal, ADC device your signal chain is equivalent to, in terms of output quality.

Let’s see this in action. Below is a signal chain involving a sensor, an amplifier, a low-pass filter, and an ADC at the end of the chain. Each of these stages contributes noise. In the example here, that noise includes thermal noise in the resistors and amplifiers of the various stages, as well as noise from external interferers, (which we call gargoyles). In this case, the gargoyles are a microprocessor clock line that’s placed too close to the signal line, causing electrical and electromagnetic interference, as well as a switching power supply also causing interference, and also causing ground plane interference.

NOTE: We aren’t showing the gargoyles in detail below. Only that they are turned on.

enob-of-a-signal-chain

Signal Chain Explorer is reporting an ENOB of 10 bits corresponding to an SNR (really SINAD) of 62 dB. This is for an input voltage in the sensor of 172.2 mVrms. So our signal chain looks like a mythical ADC that has 10 effective bits of resolution, and a full-scale voltage of 172.2 mVrms:

signal-chain-as-mythical-adc

Note that the ADC of the signal chain itself actually has an ideal resolution of 12 bits, (definition not shown), so we see how noise in the whole system degrades that ideal — from 12 bits down to 10 bits. 12-bit data words are pumped out, but on average, only 10 bits of each word has useful information.

The ENOB we just showed was for a frequency of interest (FOI) of 1 kHz. The effective number of bits actually varies with frequency, (because both the noise and signal are affected by amplifier roll-off, low pass filter roll-off, etc.), and we can see the variations by pulling up the ENOB plot in SCE. That plot shows ENOB along with the SNR (really SINAD) of the signal chain:

snr-and-enob-by-frequency

Understanding Input and Output Impedance

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In the last Short and Sweet article we talked about the input and output impedances of inverting and non-inverting op-amp stages. We sort of jumped the gun a little, because we never mentioned exactly what is meant by input and output impedance. In particular, we didn’t really explain what local impedance is. In this (not so) Short and Sweet article, we’ll do just that.

NOTE: The term local impedance is something we invented here at Robust Circuit Design. You’re not likely to find that terminology anywhere else. Local impedance simply means “the input or output impedance of a stage in a signal chain as though that stage is the only stage.” That is, we treat the stage in isolation when measuring the impedance.

First Principles

We’ll start by defining ordinary input and output impedance. We refer you to the diagram below.

definition-of-inz-and-outz-ii

Suppose you have a circuit that to you is a “black box” — you don’t know what’s inside, other than knowing that any voltage sources contained therein are set to zero volts, and any current sources are opened. Suppose the black box has a single input that you can inject a small current into and that you can then measure the resulting voltage at the input, referenced to circuit ground. Alternatively, maybe you apply a voltage and measure the corresponding current. Either way, with voltage and current in hand, the input impedance of that circuit can be calculated using Ohm’s Law:

\(\displaystyle InZ=\frac{{Vi}}{{i1}}\)

If your circuit is used as a load to another circuit, then that other circuit sees this much impedance as its load impedance.

Suppose the black box circuit has a single output (besides ground). You could inject a small current back into that output and measure the resulting voltage referenced to the circuit ground. Or alternatively you might apply a voltage and measure the corresponding current. Either way, with voltage and current in hand, the output impedance can be calculated using Ohm’s Law:

\(\displaystyle OutZ=\frac{{Vo}}{{i2}}\)

If this circuit is used as a source to another circuit, then that other circuit sees this much source impedance.

To summarize, when connecting circuits together, input impedance can become load impedance, and output impedance can become source impedance.

Your black box circuit might contain both resistive and reactive components, so the input and output impedances are in general complex variables. This means the impedances can vary by frequency.

Impedances in a signal chain

A signal chain is a series of sub-circuits arranged in a linear fashion, where a signal flows from left to right. We call the sub-circuits stages, and the first stage is normally a sensor of some kind. Here’s a diagram illustrating this:

abstract-signal-chain
In analyzing the behavior of a signal chain, it can be useful to know the input (or output impedances) at any given stage. Knowing those impedances helps us understand how the signal chain behaves at that point.

Input Impedance at a given stage

Suppose you want to know the input impedance at stage N. As illustrated below, in determining the input impedance, you must not only consider any impedances in stage N itself, but all the stages that follow:

inz-of-stage-n-fully-expanding

How do we go about doing this? Well, we could find the input impedance to stage N+1, and treat that as a “load” to stage N. For example:

inz-of-stage-n-inductively
We mentioned this idea earlier, that the input impedance of one stage can become the load impedance of another.

How do we find the input impedance of stage N+1? Well, we find the input impedance of stage N+2 and treat that as the load for stage N+1. Put that in your pipe and smoke it!

Input impedance of the last stage

We can continue this inductive process until we reach the last stage. Then we reach a boundary condition. What is the load of the last stage? Mathematically, it’s a load with infinite input impedance:

inz-of-last-stage-ii

Input impedance of single stages

The boundary condition used in computing the input impedance of the last stage can also be used to treat any stage in isolation. We pretend the other stages don’t exist. Next, we’ll look at three specific but simple cases to help you understand how this works. The three cases we consider are: (1) a series stage, (2) a shunt stage, and (3) a voltage divider stage.

Input impedance of a series stage

We’ll start with a signal chain that consists solely of a series impedance Zs:

inz-of-series-stage-ii

Our single stage, being by definition the last stage, has an implied load of infinite impedance. So what’s the total input impedance? To someone looking in from the left, it looks like an impedance Zs in series with an infinite load impedance. The end result is that the input impedance is infinite!

Can this be true? Well, a series stage all by itself is “floating”. In such a circuit, no current can flow. If this floating stage itself were to be treated as a load to another stage, since no current flows through this newly designated load, that’s the same as saying it too has infinite impedance.

Input impedance of a shunt stage

Next, we consider a shunt stage Zs all by its lonesome. Being again the last stage by definition, it’s in parallel with a load of infinite impedance:

inz-of-a-shunt-stage

To someone looking in from the left, all the input current flows through Zs, since none can flow through ZL with its infinite impedance. Thus, the input impedance of a shunt stage is the impedance of the shunt itself. We note mathematically:

\(\displaystyle Zs||ZL=\frac{{Zs\,ZL}}{{Zs+ZL}}\)

and

\(\displaystyle \underset{{ZL\to \infty }}{\mathop{{\lim }}}\,\frac{{Zs\,ZL}}{{Zs+ZL}}=Zs\)

Input impedance of a voltage divider

Next, we look at a voltage divider as our sole stage. As before, we tack on the implied infinite impedance load:

inz-of-a-voltage-divider-stage

What’s the input impedance of this stage? Any current flowing into this stage has only one way to go: through Za and Zb. No current will flow through ZL with its infinite impedance. Thus, this stage looks like Za in series with Zb.

More complicated stages

With our simple single-stage examples, you should now begin to understand how input impedance is found. Obviously more complicated stage examples could be considered, but that’s too much detail for this supposedly Short and Sweet article. But the notion of looking at series and parallel branches, and/or voltage dividers, all tacked on with an “infinite” load impedance, is the basic trick to remember.

There is, however, another concept to learn that’s directly related to our single stage configuration: local input impedance.

Local input impedance

The local input impedance of a stage is defined as the input impedance the stage would have if were the only stage in the signal chain. In other words, it’s the impedance the stage would have if it were the last stage. To repeat:

DEFINITION: Local input impedance = input impedance as if the stage were the last stage

Here’s a diagram illustrating this:

local-inz-configuration

To recap what we learned earlier about our simple single stages and how that now relates to local input impedance, we can say:

\(\displaystyle \text{Local InZ of series stage}=\infty \)

\(\displaystyle \text{Local InZ of shunt stage}=Zs\)

\(\displaystyle \text{Local InZ of voltage divider}=Za+Zb\)

Input impedance with Signal Chain Explorer

Next, we look at how to find the input impedance of any stage in an SCE signal chain. Below is an arbitrary signal chain having various stages, the first of which is a 10 Ohm series resistor stage. The left diagram shows how the series stage is selected and where to push the Local InZ button. The plot on the right is the impedance vs frequency, which in this case is just a (missing) straight line, at infinity.

series-stage-inz-plot

Here’s the same kind of thing for a 10 Ohm shunt stage. The plot shows a straight line at 10 Ohms.

shunt-stage-inz-plot

And then we have a voltage divider stage, with a series branch of 3 Ohms and shunt branch of 7 Ohms. The plot once again shows a straight line — this time at 3+4 = 7 Ohms.

vdv-stage-inz-plot

Just to remind you that impedances can be complex and vary with frequency, here’s a passive band-reject filter and it’s associated local input impedance plot:

band-reject-filter-stage

local-inz-of-band-reject-filter-ii

We have a rise in current (the turquoise line) at 60 Hz, which represents the shunting of current to ground, as by design of the stage. (The notch resonance was configured to be 60 Hz.)

This figure illustrates why we also show current on the impedance plots. The turquoise line represents the current as if a voltage of 1 V were applied at any given frequency. Due to the (linear) scale of the plot, we can’t see that the reactance is going to zero right at resonance, (which causes the current to peak), because the impedance itself shoots towards infinity at higher frequencies. But the current line is giving us a hint that something is going on at 60 Hz.

Without getting too detailed about this (we’ll save that for a later article), we can zoom in to see what’s happening. Here, the red line is reactance, the blue line resistance, and the green line the magnitude of the impedance:

local-inz-of-band-reject-filter-zoomed-in

Let’s look at this mathematically. The local input impedance of this stage is comprised of a resistor, inductor, and capacitor all in series, so:

\(\displaystyle \text{Local InZ of band reject}=R+j(\omega L-\frac{1}{{\omega C}})\)

The reactance (imaginary) term goes to zero when the terms involving L and C cancel out, which occurs right at 60 Hz in our case. The overall impedance doesn’t go completely to zero, however, because of the series resistance R. That’s why the current peak is rounded. As the frequency rises past resonance, the L term takes over, and the overall impedance goes up and up, theoretically to infinity, as you saw in the zoomed out plot.

ddda0da3-523098562 3-5409238 5-0239582 3-059238 5-023985 23-095823 -059823 098

Output Impedance at a given stage

Let’s switch gears and look at output impedance. Suppose you want to know the output impedance of stage N. As illustrated below, in determining the output impedance, you must not only consider any impedances in stage N itself, but all the stages that precede it:

outz-of-stage-n-fully-expanded

How do we go about finding this? Well, we could find the output impedance of stage N-1, and treat that as the “source” to stage N. For example:

outz-of-stage-n-inducitvely

We mentioned this idea earlier, that the output impedance of one stage can become the source impedance of another.

How do we find the output impedance of stage N-1? Well, we find the output impedance of stage N-2 and treat that as the source for stage N-1. Put that in your pipe and smoke it!

Output impedance of the first stage

We can continue this inductive process until we reach the first stage. Then we reach a boundary condition. What is the source impedance of the first stage? In SCE, the first stages are always sensor stages. Below, we’ve represented the sensor generically as an ideal voltage source along with a series impedance Zs. That impedance is the output impedance for the stage.

outz-of-sensor-stage

NOTE #1: Of course, more complicated sensor scenarios exist that we won’t go into here. And we note that in the case of current source sensors, we can just convert to the Thevenin equivalent.

NOTE #2: In keeping with how impedances are determined, we set the sensor voltage to zero when finding the output impedance.

Suppose the sensor has no series impedance. Then what impedance do we use for the stage? Well, we have the ideal voltage source, which by definition has an output impedance of zero.

NOTE: If you use a current source for your sensor, then it may be of interest for you to know that the output impedance of an ideal current source is infinite.

Output impedance of single stages

If we wanted to find the output impedance of a signal chain having only one stage and that stage wasn’t a sensor, then what do we do? Merely pretend that the stage has an ideal voltage source attached to it, as we show below. The source impedance coming in to our stage is thus zero.

outz-of-first-stage-ii

As always, we must set the voltage of the source to zero in order to find the stage impedance.

Note the symmetry between input and output impedance: For input impedances, the last stage has an implied load with infinite impedance. For output impedances, the first stage has an implied voltage source in front of it, (that we set to zero), with zero impedance. This is summarized in the following diagram, which we show for a signal chain having only one stage:

single-stage-impedance-symmetry-ii

Next, we’ll look at three specific but simple cases to help you understand how this works. The three cases we consider are: (1) a series stage, (2) a shunt stage, and (3) a voltage divider stage.

Output impedance of a series stage

We’ll start with a signal chain that consists solely of a series impedance Zs:

outz-of-a-series-stage

Our single stage, being by definition the first stage, has an implied voltage source of zero impedance. So what’s the total output impedance? To someone looking in from the right, it looks like an impedance Zs in series with a zero source impedance. The end result is that the output impedance is the impedance of the stage itself.

Output impedance of a shunt stage

Next, we consider a shunt stage Zs all by its lonesome. Being again the first stage by definition, it’s in parallel with a voltage source having zero impedance:

outz-of-a-shunt-stage

To someone looking in from the right, all the current flows through the voltage source branch, since it’s a short! So the output impedance is zero.

Output impedance of a voltage divider

Next, we look at a voltage divider as our sole stage. As before, we stick an ideal voltage source on the front:

outz-of-a-voltage-divider

What’s the output impedance of this stage? Any current flowing into this stage from the right has two pathways to ground: through Za and Zb. That is, we have a parallel configuration. So the output impedance is the parallel impedance of the two branches.

More complicated stages

With our simple single-stage examples, you should now begin to understand how output impedance is found. Obviously more complicated stage examples could be considered, such as a closed-loop amp stage, which we’ll see later. In general, though, it’s too much detail for this Short and Sweet article, but the notion of looking at series and parallel branches, with a zero source impedance tacked on front, is the basic trick to remember.

There is, however, another concept to learn that’s directly related to our single stage configuration: local output impedance.

Local output impedance

The local output impedance of a stage is defined as the output impedance the stage would have if were the only stage in the signal chain. In other words, it’s the impedance the stage would have if it were the first stage. To repeat:

DEFINITION: Local output impedance = output impedance as if the stage were the first stage

Here’s a diagram illustrating this:

local-outz-of-a-stage

To recap what we learned earlier about our simple single stages and how that now relates to local output impedance, we can say:

\(\displaystyle \text{Local OutZ of series stage}=Zs\)

\(\displaystyle \text{Local OutZ of shunt stage}=0\)

\(\displaystyle \text{Local OutZ of voltage divider}=\frac{{Za\,Zb}}{{Za+Zb}}\)

Output impedance with Signal Chain Explorer

Next, we look at how to find the output impedance of any stage in an SCE signal chain. Below is an arbitrary signal chain having various stages, the first of which is a 10 Ohm series resistor stage. The left diagram shows how the series stage is selected and where to push the Local OutZ button. The plot on the right is the impedance vs frequency, which in this case is just a straight line at Zs = 10.

series-stage-outz-plot

Here’s the same kind of thing for a 10 Ohm shunt stage. The plot shows a straight line at 0 Ohms.

shunt-stage-outz-plot

And then we have a voltage divider stage, with a series branch of 3 Ohms and shunt branch of 7 Ohms. The plot once again shows a straight line — this time at (3 x 4) / (3 + 4) = 1.714 Ohms.

vdv-stage-outz-plot

Just to remind you that impedances can be complex and vary with frequency, here’s a passive band-reject filter and it’s associated output impedance plot:

band-reject-filter-stage-outz

We have a notch right at 60 Hz, as by design of the stage. (F resonance was set to 60 Hz.)

local-outz-of-band-reject-filter-ii

Op-amp stage local output impedance revisited

In the last Short and Sweet article we discovered that the local output impedances of a gain follower (aka non-inverter) and an inverter stage were identical, given the same amplifier and the same external resistance values. To refresh your memory, here are the two plots:

gain-follower-outz-plot-iii

gain-follower-outz-plot-ii

To see why this is so, reconsider the definition we gave for local output impedance: It’s the output impedance the stage would have if it were the first stage. Being the first stage, it’s implied that there’s a voltage source in front, with zero voltage and zero impedance. For a gain follower stage, that voltage source is driving the positive pin of the op-amp. For an inverter, it’s driving the negative pin. In both cases, the non-signal pin goes to ground. It’s possible to draw both of these stages using the same circuit topology but with a different signal orientation, and in doing so, we’ll also put in these voltage sources that are set to zero:

local-outz-dualism-of-op-amp-stage-iv

If A is the signal line, then we have an inverter. If B is the signal line, we have a non-inverter (gain follower). Either way, when we determine local output impedance, we set the associated voltage sources (the “signals”) to zero, and you can see by inspection that we have the same circuit. That means the local output impedances will be the same.

Just in case you want to know what that local output impedance is, here’s the formula in all its glory, where G(jω) is the open-loop gain of the op-amp, which varies by frequency:

\(\displaystyle LocalOutZ=\frac{{(Rf\,Rg+Rf\,Rin+Rg\,Rin)Roa}}{{Rf\,Rg+Rf\,Rin+Rg\,Rin+G(j\omega )Rg\,Rin+Rg\,Roa+Rin\,Roa}}\)

That varying open-loop gain serves to give the amp stages an inductive behavior on the output at intermediate frequencies.

Summary

You’ve seen how to think about input and output impedances, particularly as they pertain to linear signal chains. And you’ve been introduced to the concept of the local input and output impedance of a stage, which is derived by pretending the stage is the only one in the signal chain. Summarizing, local input impedances are found by setting the load of the stage to have infinite impedance. Local output impedances are found by setting the source of the stage to have zero impedance. We repeat a diagram we gave earlier to help you remember:

single-stage-impedance-symmetry-ii

Armed with this knowledge, you are now ready to explore signal chains in Signal Chain Explorer and see what sort of mysteries you can uncover by examining the interactions between the stages, by way of both local and overall impedances. With Signal Chain Explorer, visualizing these impedances takes just a single click.

Visualizing Op Amp Impedances using SCE

Robust Circuit Design Posted on by

One of the unique and powerful features of Signal Chain Explorer is the ability to quickly see the input and output impedances of a stage, both “locally” (stage by itself) and “globally” (backwards or forwards to the beginning or end of the signal chain.) The former we call “local impedance.” The latter, global impedance. We showcased global impedance in an earlier article LC Baluns in Action. If you haven’t read that article, you should check it out. You’ll get to see how valuable it is to be able to easily and graphically verify that the LC Baluns are doing the impedance matching they were designed to do.

Now, in this Short and Sweet article we take a look at input and output impedance as they pertain to op-amp stages. If you’ve never had the opportunity see these amp stage impedances visually, you might be surprised by the results.

The impedance buttons

Before we get started, we want to point out where the buttons are that allow you to see the various types of impedance. They are located just above the signal chain panel:

the-impedance-buttons

NOTE: If you are following along with this article by running SCE, pay very close attention to which impedance buttons you push. The local impedance buttons return very different results from the global impedance buttons. And be careful which stage is selected. Don’t be fooled!

UA741 gain follower (non-inverting stage) impedance

We’ll start by adding a closed-loop voltage gain follower stage to a signal chain, and then look at its local input and output impedances. The stage circuit is as follows:

ua741-gain-follower-stage
Here, we’re using a UA741 op amp, along with a closed loop feedback resistance of 10 K and shunt resistance of 1 K. We’ve annotated two key features of the op-amp as pertains to impedance: The amp’s input resistance Rin (the differential input resistance) and the open loop output resistance Roa. While many are familiar with the high input resistances of op amps (in this case, 2 MOhms), the other end of the amp, the output resistance, (in this case, 75 Ohms), often gets ignored. But you’ll learn in this and other articles to come that you should definitely pay attention to Roa.

NOTE: If you don’t want surprises in your signal chains, knowing the output resistance is a very valuable piece of information to have, but finding its value can be tricky, as datasheets for op-amps may not specify it directly, but may infer it with graphs, and/or specify instead the closed loop output impedance (which we will be illustrating in this article) at one or more frequencies. In an article to come, we’ll show how you can determine the open loop output resistance both from datasheets, and by testing on the bench.

Here’s how the UA 741 gain follower is set up in SCE. Note the open loop gain of 106 dB, and closed loop gain of around 21 dB set by the external resistors. This op-amp has a unity gain bandwidth of 1 MHz, and an open loop corner frequency of 5 Hz:

gain-follower-stage-definition

Gain follower input impedance

When it comes to impedance, you might think that the 2 MOhms input resistance is all you need to know when interfacing to the inputs of this op-amp. But that is decidedly not the case! You may not realize that the input resistance of a closed-loop op-amp stage varies significantly with frequency, as shown in the plot below, which was produced by clicking on the Local InZ button with the gain follower stage selected as the stage of interest. The green curve, the magnitude of the impedance, is mainly what we are focusing on:

gain-follower-inz-plot

At low frequencies, the input impedance is much higher than 2 MOhms — it’s roughly 36 GOhms! Why? Because of the closed loop behavior of the circuit. When there is plenty of op-amp gain to spare, the circuit tries to force the input and output pins to the same voltage. In doing so, the input impedance rises significantly, being multiplied in part by the op-amp gain. Were the op-amp to be ideal, with infinite DC gain, the input impedance would be infinite as well. This can be seen in the following equation, which shows the formula for the input impedance of our stage at DC. Here, D is the open-loop DC gain of the op-amp:

\(\displaystyle GF InZ(DC)\,=Rin+\frac{{Rg\left( {Rf+D\,Rin+Roa} \right)}}{{Rf+Rg+Roa}}\)

You can easily see that as D goes to infinity, so does this term.

However, as the frequency increases, another term is subtracted from the DC impedance term, where s is the Laplace frequency variable and U is the unity gain frequency:

\(\displaystyle \frac{{{{D}^{2}}Rg\,Rin\,s}}{{\left( {Rf+Rg+Roa} \right)\left( {Ds+U} \right)}}\)

This subtracted term causes the capacitive-like roll off of the impedance (realize that the impedance plots are linear in Y), until the impedance settles on the 2 MOhm input resistance, which occurs out past where the op-amp can no longer deliver gain (ie., past the unity gain frequency). The following zoomed in plot shows this:

gain-follower-outz-closeup

We aren’t usually privy to such detailed equations as shown earlier when thinking about op-amp behavior, but that’s okay, SCE’s impedance plots show us what will happen anyway, and these graphical plots are very informative. We note with interest from the original InZ plot that the reactance bottoms out right at the op-amp’s corner frequency of 5 Hz. We don’t know what that implies.

We recap the behavior of a gain follower: At DC, a gain follower has very high impedance. At intermediate frequencies, the stage input looks like a capacitor. A high frequencies, the stage takes on the input impedance of the op-amp itself.

Gain follower output impedance

The following plot shows the local output impedance of our gain follower stage:

gain-follower-outz-plot-iii
As was the case with input impedance, the output impedance of a closed loop gain follower varies by frequency, due to the closed-loop behavior of the stage. At low frequencies, our stage has very low output impedance — a desirable quality that makes the device easy to use, with minimal losses. However, at intermediate frequencies, the stage looks more like an inductor, the consequences of which we’ll explore in a bit. At high frequencies, out above unity gain, the stage takes on the open-loop resistance of the op-amp itself.

Beware the output resistance!

Because of the inductive behavior of the output impedance of a closed-loop gain follower stage, you must be careful when hanging non-resistive loads on the output. For example, should you have a capacitive load, it will combine with the inductive behavior to create in effect a second-order system, and as you might be aware, such systems can have resonant peaking, and can even oscillate out of control.

For example, let’s put a 10 uF capacitor shunt after the gain follower stage:

addition-of-a-capacitor-stage

Here’s the resulting Bode plot. Notice the classic second order response, and the 25 dB of peaking.

capacitive-load-peaking

Isolation Effects of a Gain Follower Stage

It’s well known that gain follower stages (remember, another name of non-inverter) are good at isolating one side of your signal chain from the other. In this section, we’re going to see this graphically, using the global impedance buttons, as opposed to the local impedance buttons.

Below is a signal chain consisting of a phono cartridge sensor having 1,550 Ohms series resistance and 650 mH of series inductance, (you saw this sensor in use in the posts Simple Digitized Audio Example and Upgrades to the Sensor Stages of Signal Chain Explorer), followed by a parallel RC shunt stage of 47 kOhms and 200 pF. Following this is a gain follower stage.

Let’s first see what the overall output impedance is of the circuit consisting of just the sensor and RC shunt stage, without the amplifier stage. We can do this by selecting the shunt stage to be our current “stage of interest”, and then clicking the global OutZ button. This has the effect of showing the output impedance by looking backwards from the shunt stage to the sensor stage.

Below is the arrangement of our signal chain and how we select the appropriate stage and use the appropriate output impedance button:

setting-up-global-output-impedance-plot

Here’s what we get for output impedance:

output-impedance-after-shunt-stage-ii

There are some interesting things going on around 11 kHz. Let’s see what happens if we use our gain following to isolate the rest of the signal chain from this. To do so, select the gain follower stage as the “stage of interest” and press the global OutZ button:

setting-up-overall-global-output-impedance-plot

Here’s the resulting impedance plot:

overall-output-impedance-of-gain-follower-stage

It’s the same plot we saw earlier for the “local” input impedance of the amplifier stage. So the gain follower does a good job of isolating any stages to the right (we have none in our example) from the effects of the phono cartridge and termination shunt stages to the left.

UA741 inverter stage impedance

Now it’s time to switch gears and look at the impedances of an inverter stage. We’ll use the same UA741 op-amp as before, and the same feedback resistor of 10 kOhm, and we’ll use a 1 kOhm input resistor:

ua741-inverter-stage

The following figure shows the setup in SCE:

inverter-stage-definition

Inverter local input impedance

Okay, what do you suppose the input impedance of our inverter stage is? 2 MOhm? 36 GOhm like we got for the gain follower?

How about 1 kOhm — at least at low frequencies. The following plot tells the tale:

output-impedance-of-an-inverter-stage
At low frequencies, the input impedance is simply the resistance of our input resistor of 1 kOhm. But then, at intermediate frequencies, the impedance rises with an inductive-like behavior, and then eventually settles to 11 kOhm. Note that 11K = 1 K + 10K = Rn + Rf.

This is a very different plot from our gain follower input impedance, which started very high, went capacitive, and then settled to the input resistance of the op-amp itself. With the inverter, the input resistance of the op-amp is out of the picture. Why? Hmm…, looks like another article is in order, and we’ll leave that for another day.

We note with interest the reactance peaks at 1 MHz, the unity gain frequency of our op-amp. We don’t know the implications of that.

Inverter local output impedance

Okay, now let’s see what the local output impedance of this puppy looks like:

gain-follower-outz-plot-ii

Interestingly enough, it’s identical to the output impedance of our gain follower stage! Hmmm, wonder why that is. (Maybe we’ll investigate this too in another article.)

But what about the isolation characteristics of our inverter? Will it isolate the stages to the right from the stages to the left? Let’s find out. Remember our signal chain earlier, where we had a phono cartridge sensor and then a shunt termination stage before the gain follower? We could build the same circuit, but use an inverter instead, and then look at the overall output impedance. The figure below shows the result:

overall-output-impedance-of-an-inverter-amplifier-chain

Yikes! We can see the effects of the phono cartridge “bleed through”. How does this occur? There is a direct path from input to output in the inverter stage, passing through Rn and then Rf, but not needing to pass through the op-amp at all. That’s how the stages to the left of the amp stage can affect the stages to the right.

We’re sure there’s plenty more we could investigate right here about op-amp impedances and the like, but we’ll leave that for another day and dollar. Besides, this Short and Sweet article is getting a bit long.

But don’t let that stop you from further exploration using the unique and valuable impedance plots of Signal Chain Explorer! We hope you realize that you can use the local and global impedance plots at any stage of any signal chain, even complicated ones. We think being able to easily visualize the impedance functions will prove to be a powerful tool.

My KT lies over the C (Part 2)

Robust Circuit Design Posted on by

In Part 1 of this Short and Sweet article we derived the formula for thermal noise as it applies to RC filter circuits:

\(\displaystyle {{\eta }_{v}}^{2}={{KT}}/{C}\;\)

In this blog post, we’ll try out various RC filters using Signal Chain Explorer and see if this formula holds. While the formula was developed for low pass RC filters, it also works for other first order RC configurations as you’ll see.

Putting SCE to the test

Below is a screenshot of a signal chain we created in SCE consisting of a sensor (just a voltage source) and a low pass filter stage. For illustration purposes, we’ve set up a simulation frequency range of 100 mHz to 1 GHz, and we are purposely using a coarse simulation resolution of 2 bands/decade. For our filter, we’re using R = 10 Ohms, and C = 10 pF.

lp-screenshot

This filter has a corner frequency of 1.59 GHz as shown in the low pass filter worksheet. It also has an effective noise bandwidth (not shown) of:

\(\displaystyle {{f}_{{enbw}}}=\frac{1}{{4RC}}=\frac{1}{{4\times 10\times 10\times {{{10}}^{{-12}}}}}=2.5\,GHz\)

When we press the main Update button , SCE computes the integrated thermal noise of our filter and comes up with 15.1 uVrms, as indicated on the screenshot. Is this correct?

Well, from the KT/C formula, we can compute the theoretical amount:

\(\displaystyle {{\eta }_{v}}=\sqrt{{\frac{{KT}}{C}}}=\sqrt{{\frac{{1.38064852\times {{{10}}^{{-23}}}\times 290}}{{10\times {{{10}}^{{-12}}}}}}}=20\mu Vrms\)

NOTE #1: In case you are wondering, thermal noise voltage is specified as an RMS value. That’s because it’s actually a statistical value, as we noted in Part 1.

NOTE #2: SCE defaults the ambient temperature used in noise calculations to 290 degK.

Hmm, 20 != 15.1. Seems like SCE is plain wrong. Guess we should just delete the program off our system.

Please don’t do that! It’s only wrong because we didn’t use it right. And two wrongs don’t make a right. But what are the two wrongs?

  1. We didn’t use enough resolution in our simulation, as indicated by the lowly 2 bands/decade. We’ll get back to that in a bit.
  2. The reported thermal noise is the total integrated noise voltage over whatever frequency range we happened to pick for the simulation — in this case, 100 mHz to 1 GHz. But we didn’t cover a wide enough frequency range. We know this because the corner frequency for our filter is 1.59 GHz, and we’re only going out to 1 GHz. Not to mention the fact that we already know that the effective noise bandwidth is 2.5 GHz, and we haven’t covered that either. In fact, we’ll have to go out much further than the effective noise bandwidth. We can see this if we pull up the thermal noise plot by clicking the icon to the right of the overall thermal noise value on the main screen:

 

2016-10-27-3

This is a plot of the thermal noise voltage by frequency “bands.” For each band, we compute the thermal noise for each noise source using the formula \(\displaystyle {{\eta }_{v}}=\sqrt{{4KTBR}}\), and for B we use the bandwidth of the band. Then, reminiscent of Part 1, we sum up those individual noises and come up with an integrated value.

NOTE: See Understanding SCE Thermal Noise Charts for more detail on how the thermal noise plots are produced.

The thermal noise plot is log-linear: the horizontal frequency axis is logarithmic, and the vertical noise voltage axis is linear. Because of the logarithmic scale, each band covers a progressively wider range of frequencies, as we go up in frequency. And a wider band means more noise. That’s why the plot is rising, even though as we noted before, thermal noise is “white”, and has a flat spectrum (if not filtered). That flatness is only true if the spectrum is shown linearly, rather than logarithmically as is done here.

From the rising plot we get the hint that maybe we aren’t seeing all of the thermal noise, and that’s a problem. For the integrated noise voltage computed, (the area under the curve so to speak), SCE uses only the frequency range selected — in this case from 100 mHz to 1 GHz. Let’s see what happens if we go out to a 100 THz instead. (Hey, this is math. We can do whatever we want! 🙂

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Looks like we’re covering an adequate frequency range now — we seemed to have captured all of the noise. So now our total integrated noise comes out to 20.5 uVrms, as indicated in the top right-hand corner of the plot.

Better. But 20.5 uV still doesn’t equal 20 uV, our theoretical number. Is the theory wrong? Is SCE simply not accurate enough? Nope on both counts. As you might have guessed from our rather coarse plot, we need to give the simulation more resolution. Let’s see what happens if we change the bands/decade from 2 to 20:

thermal-noise-plot-for-lp
Now we get our fabled 20 uV. Yay!

NOTE #1: Our plot only reports a few significant digits in its results, so we may not be exactly at 20 uV, but it’s close enough for demonstration purposes.

NOTE #2: In case you are wondering, the thermal noise plots are showing noise voltage, and not noise power as we saw in Part 1 when we derived the KT/C formula. Also, the noise power plots were linear, whereas our thermal noise plots are log-linear. Because of these two reasons, the shapes of the two plots don’t come out the same. Not to worry, for we are indeed doing a integration of sorts when we compute thermal noise. We are adding up the noise voltages in all the bands, using a root-sum-square approach.

Reminder: For more information on how the thermal noise plots work, see the blog post we mentioned earlier: Understanding SCE Thermal Noise Charts.

Other RC circuits

So you’ve seen that the KT/C formula works for low-pass RC filters, and we’ve confirmed it in SCE. But what about high-pass RC filters? What about parallel RC filters? We can construct such filters in SCE and find out! That’s what Signal Chain Explorer is all about — exploring. We’ll use the same R and C values as before, and we’ll use the 100 mHz to 100 THz frequency range that we settled on earlier, along with 20 bands/decade. The results for these other filter configurations are summarized in the following figures:

thermal-noise-plot-for-hpParallel RC version

thermal-noise-for-parallel-rc-ii

thermal-noise-for-parallel-rc-norton-version

These results might seem surprising at first. All of the circuits have exactly same thermal noise, even down to the shape of the thermal noise plots themselves. Wow!

There’s a reason why this is so. As far as computing thermal noise referred-to-output is concerned, our circuit configurations all map to the same circuit — basically a parallel RC. We illustrate this below. In all of these circuits we set the voltage source to zero so that we can then find Verr referred to output (which is Vo).

Note that for the circuit involving the current source (D), we can convert it to its Thevenin equivalent, and see that it matches the circuit right above it (C). Thus, the current source version will have the same Verr referred to output.

equivalent-rc-circuits-ii

My KT lies over the C (Part 1)

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My Bonnie lies over the ocean. My KT lies over the C …

Okay, with that lame joke out of the way, in Part1 of this (perhaps not so) Short and Sweet two-part article, we’ll derive the well-known  \(\displaystyle {{\eta }_{v}}^{2}={{KT}}/{C}\;\) equation, relating thermal noise to first order circuits involving capacitors. In Part 2 we’ll test out the equation using Signal Chain Explorer. By doing this we can accomplish two things:

(1) We can confirm that the underlying thermal noise calculations used in SCE are indeed correct,

and

(2) we can better relate the noise voltage integration by comparing the thermal noise plots automatically generated in SCE with the actual circuit response.

Wait. Capacitors have noise? No, not really.

When it comes to noise involving capacitors, you may already be familiar with our featured formula:

\(\displaystyle {{\eta }_{v}}^{2}={{KT}}/{C}\;\)

where  \(\displaystyle {{\eta }_{v}}\) is thermal noise voltage.

This formula seems to imply that capacitors have thermal noise. But that isn’t the case. Capacitors don’t have thermal noise (well, at least ideal ones don’t). Instead, the formula is meant to be applied only to certain circuits — first order networks with a resistance R and capacitance C. It really is the resistance that contributes the noise, but it just so happens that if you derive the thermal noise of that resistance and refer it to output, the resulting formula has the resistance cancelling out, and you are left with the famous KT/C equation.

In this article we’ll see how that comes about. To begin, we’ll start at ground zero and remind you of another famous formula for determining thermal noise power:

\(\displaystyle {{\eta }_{p}}=\frac{{{{\eta }_{v}}^{2}}}{{4R}}=KTB\quad \{W\}\)

or stated in terms of noise voltage,

\(\displaystyle {{\eta }_{v}}=\sqrt{{4KTBR}}\quad \{V\}\)

Here, K is Boltzmann’s constant, equal to 1.38064852e-23 J/degK, T is the temperature of the system, B is the bandwidth of the system in Hz, and R is the resistance.

NOTE: You might wonder where the factor 4 comes from. That’ll be explained in another article!

What is the bandwidth B of which we speak? We’ll get to that in a minute, but before we do, let’s remove it from our equation! We do this by dividing it out and coming up with noise power density, and its cousin, noise voltage density. These have units of \(\displaystyle {W}/{{Hz}}\;\) and \(\displaystyle {V}/{{\sqrt{{Hz}}}}\;\), respectively.

\(\displaystyle {{\eta }_{{pd}}}=\frac{{KTB}}{B}=KT\quad \{{W}/{{Hz}}\;\}\)

\(\displaystyle {{\eta }_{{vd}}}=\frac{{\sqrt{{4KTBR}}}}{{\sqrt{B}}}=\sqrt{{4KTR}}\quad \{{V}/{{\sqrt{{Hz}}\}}}\;\)

Now that we’ve removed bandwidth, let’s see why we should be concerned with it anyway! It turns out that thermal noise is random, in a Gaussian sort of way. (It should be noted that the power and voltage terms above are RMS values that relate to thermal noise’s statistical nature). Thermal noise is called white noise because it has the same RMS amplitude at all frequencies. (Well, at least up to the THz region.)

Any circuit that has resistance will have thermal noise, but due to the frequency response of the circuit, that noise will be modulated as a function of frequency. Let’s call that modulation function \(\displaystyle H(j\omega )\). We can plot the resulting noise power density vs frequency by using the square of \(\displaystyle H(j\omega )\), and then we can compute the overall noise power by chopping up the curve in the frequency domain into tiny slices and integrating. The figure below illustrates this process:

integrated-noise-density-plot-iv

The area under this curve, that we get by integration, is the total noise power — an important value to know as it can greatly affect signal quality.

NOTE: We are using angular rad/s frequency above, even though the thermal noise power and voltage functions uses Hz. Don’t be confused. We’ll convert back to Hz when appropriate.

In dealing with the noise formula, it’s often useful to have a single bandwidth value to work with. We can define such a number, called the effective noise bandwidth, if we happen to know the total noise power for a given temperature and resistance — we just use an inversion of the KTB formula:

\(\displaystyle \text{Effective noise bandwidth }B=\frac{{{{\eta }_{p}}}}{{KT}}\quad \{Hz\}\)

One way to think of this bandwidth is in terms of a brickwall filter. Such a filter has an output gain of one (that is, no attenuation) in its passband, and zero (complete annihilation) elsewhere. For a brickwall filter, the width of the passband is the effective noise bandwidth, by definition. The following plot illustrates:

brickwall-filter-noise-power-density

To determine the effective noise bandwidth of an arbitrary filter, the trick is to compute the area under the power density curve like we did earlier, and then find a brickwall filter that has the same area. The bandwidth of that brickwall will be our effective noise bandwidth. The figure below illustrates this for a low pass filter, along with its brickwall counterpart:

equivalent-noise-density-curve-areas

The bandwidth of the area in orange is the effective noise bandwidth of the low pass filter. In the example above, we’re using a low pass filter consisting of a 10 Ohm resistor and a 10 pF capacitor. This circuit has an effective noise bandwidth of 15.71 Grad/s (2.5 GHz). Next, we’ll see how to compute this.

Effective bandwidth formula

Given below is a formula for calculating the effective noise bandwidth of any filter utilizing noise power densities. It shouldn’t be too surprising, as we’ve already talked about integrating the density curve.

\(\displaystyle {{\omega }_{{enbw}}}=\int_{0}^{\infty }{{{{{\left| {\frac{{H(j\omega )}}{{{{H}_{{\max }}}}}} \right|}}^{2}}d\omega }}\)

Here, \(\displaystyle {{\left| {H(j\omega )} \right|}^{2}}\) is the absolute value of the filter’s noise power gain as a function of frequency divided \(\displaystyle {{{H}_{{\max }}}}\), its maximum. (In essence, we’re scaling to get relative power.)

To see this in action, we’re going to use this integral to calculate the effective noise bandwidth of a low pass filter. To do so, we’ll need to derive the thermal noise power gain function for that filter.

Noise power gain for a low pass filter

Given a thermal noise voltage associated with a resistor in a low pass configuration, let’s derive the value of that noise voltage referred to output. That will be \(\displaystyle {H(j\omega )}\), which represents how much that voltage is modulated at the output. Squaring that function gives us the noise power gain.

Here’s a diagram illustrating a voltage source and low pass filter. The thermal noise voltage generated by the resistor is represented by Verr, and we place it in series with the resistor. In this circuit, we set the source voltage to zero as part of the derivation for the referred-to-output noise voltage. This is in keeping with general circuit theory involving linear superposition:

lp-verr-rto

What we’re looking for is the value of the output voltage Vo in terms of Verr, R, and C, and then we can take the ratio Vo / Verr. This gives us our desired gain function. We can derive this by using the voltage divider relation given below, where A is the generic series branch impedance, and B is the generic shunt branch impedance:

\(\displaystyle Vo=Verr\times \frac{B}{{A+B}}\quad \Rightarrow \quad H(j\omega )\equiv \frac{{Vo}}{{Verr}}=\frac{B}{{A+B}}\)

For a low pass filter, A = R, and B = 1/(C s) — the impedance of a capacitor in the Laplace domain. Plugging these values into our formula and staying in the Laplace domain, we can derive:

\(\require {cancel} \displaystyle H(s)=\frac{{{1}/{{\cancel{{Cs}}}}\;}}{{R+{1}/{{\cancel{{Cs}}}}\;}}\times \frac{{\cancel{{Cs}}}}{{\cancel{{Cs}}}}=\frac{1}{{1+RCs}}\)

Substituting \(\displaystyle s\to j\omega \), we end up with:

\(\displaystyle H(j\omega )=\frac{1}{{1+RCj\omega }}\)

For the effective noise bandwidth integral, we’ll be needing the noise power gain, which we can obtain by squaring the result we just obtained:

\(\displaystyle {{\left| {H(j\omega )} \right|}^{2}}={{\left| {\frac{1}{{1+RCj\omega }}} \right|}^{2}}=\frac{1}{{1+{{R}^{2}}{{C}^{2}}{{\omega }^{2}}}}\)

Note that at DC (\(\displaystyle \omega =0\)) we have maximum gain, so

\(\displaystyle {{H}_{{\max }}}={{\left. {\frac{1}{{1+{{R}^{2}}{{C}^{2}}{{\omega }^{2}}}}} \right|}_{{\omega =0}}}=1\)

Now we are ready to compute the noise bandwidth:

\(\displaystyle {{\omega }_{{enbw}}}=\int_{0}^{\infty }{{{{{\left| {\frac{{H(j\omega )}}{{{{H}_{{\max }}}}}} \right|}}^{2}}d\omega }}=\int_{0}^{\infty }{{\frac{1}{{1+{{R}^{2}}{{C}^{2}}{{\omega }^{2}}}}d\omega }}=\left. {\frac{{{{{Tan}}^{{-1}}}(RC\omega )}}{{RC}}} \right|_{0}^{\infty }\)

Evaluating our result at infinity and zero, and noting that \(\displaystyle {{Tan}^{{-1}}}(\infty )={\pi }/{2}\;\) and \(\displaystyle {{Tan}^{{-1}}}(0)=0\), we end up with:

\(\displaystyle {{\omega }_{{enbw}}}=\frac{\pi }{2}\frac{1}{{RC}}-0=\frac{\pi }{2}\frac{1}{{RC}}\)

In a first order RC system, the corner frequency is defined as

\(\displaystyle {{\omega }_{c}}=\frac{1}{{RC}}\)

With this, we can write the effective noise bandwidth as:

\(\displaystyle {{\omega }_{{enbw}}}=\frac{\pi }{2}{{\omega }_{c}}\)

This last formula is worth remembering anytime you need to know the effective bandwidth of your RC filter.

Final steps

Our effective noise bandwidth as just derived has units of rad/s. You’d have to convert to Hz to use it in the thermal noise equation. Here’s the derivation:

\(\displaystyle {{\omega }_{{enbw}}}=\frac{\pi }{2}{{\omega }_{c}}\)

\(\displaystyle 2\pi {{f}_{{enbw}}}=\frac{\pi }{2}{{\omega }_{c}}\)

\(\require {cancel} \displaystyle {{f}_{{enbw}}}=\frac{{\cancel{\pi }}}{2}{{\omega }_{c}}\times \frac{1}{{2\cancel{\pi }}}=\frac{{{{\omega }_{c}}}}{4}\)

Plugging in the formula for the corner frequency,

\(\displaystyle {{\omega }_{c}}={1}/{{(RC)}}\;\)

into the equation for \(\displaystyle {{f}_{{enbw}}}\), we obtain

\(\displaystyle {{f}_{{enbw}}}=\frac{{{{\omega }_{c}}}}{4}=\frac{1}{{4RC}}\)

With this last equation, we’re almost at the finish line, ready to derive the noise voltage for a low pass filter. All need to do is plug this formula for effective bandwidth into the formula for thermal noise power. That is, we set \(\displaystyle B={{f}_{{enbw}}}\). So we can write:

\(\require {cancel} \displaystyle {{\eta }_{v}}^{2}=4KTBR=\bcancel{4}KT\frac{1}{{\bcancel{4}\bcancel{R}C}}\bcancel{R}=\frac{{KT}}{C}\)

or

\(\displaystyle {{\eta }_{v}}=\sqrt{{\frac{{KT}}{C}}}\)

Voila! It’s magic! Our resistance R has disappeared. And we’ve managed to confirm that, yes, our KT really does lie over C.

Why does R disappear? Well, when R goes up, the noise voltage generated by R goes up too, but the gain function causes that voltage, referred to output, to be attenuated at lower frequencies than it would have otherwise. The effective noise bandwidth, used in deriving KT/C, encapsulates this balancing act.

In Part 2 of this Short and Sweet article, we’re going to put this formula to the test using Signal Chain Explorer. A key feature of SCE is that it computes thermal noise automatically. We can see if, for a low pass filter, we get the predicted results. The answer will be yes, and you’ll see that this formula works for other related RC circuits as well.

Upgrades to the Sensor Stages in Signal Chain Explorer

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The most recent versions of Signal Chain Explorer (SCE) have seen upgrades to the sensor stage library. SCE now has three types of sensors, all general in nature, and all meant to allow you to model a variety of basic sensor configurations by choosing appropriate parameters. The three types are:

  • Voltage based sensors
  • Current based sensors
  • Charge based sensors

In this post, we give an overview of these sensor types. We hope to have articles that go into more detail in the future.

NOTE: While the current crop of sensors have only single-ended outputs, we are working on sensor stages with differential outputs, but they’re not ready yet. Also, the three sensor types given here form the nucleus of more complex and specific configurations. We’ll be adding more sensor stages along these lines as times goes by.

Voltage Based Sensors

voltage-based-sensor

A voltage based sensor has a voltage source as its input signal. For convenience, you can optionally specify a series resistance, series inductance, and a capacitor shunt to ground. Next, we’ll show a few examples.

Guitar Pickup

A guitar pickup can be modeled using a voltage based sensor stage. Such a pickup has one or more bobbins of wound wire surrounding magnetic poles, usually one per string, and the pickup works by magnetic induction. Vibrating guitar strings cause a voltage to be generated in the pickup. A typical voltage range is in 100s of millivolts to a volt or so. In simple models of a guitar pickup, all three types of impedance are present: series resistance, series inductance, and shunt capacitance. In these simple models, the pickups have two poles in their response (they are second order). Because of this, they exhibit a resonant frequency. Below is an example of a Stratocaster type guitar pickup:

2016-10-24-7

Here’s how we might model this in SCE:

stratocaster-pickup-example-iii

We’ve arbitrarily set the input voltage to 400 mV, but it’s not a bad place to start for such a pickup.

NOTE: For all sensors stages of SCE, we pretend the specified signal voltage applies for any signal frequency we happen to use during the frequency sweeps of the simulation.

Here’s a bode chart that shows the second order response of our pickup, which has a resonant frequency around 11 kHz. Most guitar pickups resonate in the 5-15 kHz range, and it’s common for electric guitars have tone circuits and controls to help tame this resonance and shape the characteristic sound of the guitar. Proper specification of cables, termination shunts, etc, come into play for this as well.

stratocaster-bode
Phono Cartridge

Another example of a voltage based sensor is a phono cartridge pickup, which involves a magnet and a coil. Either the magnet or the coil moves due to needle vibrations. Here, we’ll show an example of a moving magnet cartridge — a Shure M97xE.

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This cartridge generates on the order of 4 mV peak (depends of course on the passage of music), and the cartridge has both series resistance and inductance, as shown in the following stage definition in SCE:

2016-10-21-1

The Shure M97xE spec sheet shows the cartridge having 1550 ohms of series resistance, and 650 mH of inductance. No capacitance value is specified, so in the stage definition, we have unchecked the capacitor entry. This has the effect of leaving the shunt branch open.

Phono cartridges must be properly terminated. A typical thing to do for these types of cartridges is to terminate them with a parallel resistance and capacitance shunt, using 47 kOhms and several hundred pF (some of which might be in the wiring from the cartridge to the termination shunt.) Here is the definition of a typical phono cartridge shunt stage in SCE:

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Below is the bode chart of the cartridge and termination shunt. Properly terminated, no peaking is exhibited in the response, even though we have a second order system with both inductance and capacitance. There is about 6 dB of rolloff at 20 kHz, and thereafter starts the 40 dB/decade rolloff indicative of a second order system.

2016-10-21-4

Current based sensors

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A current based sensor has a current source as its input signal. Rather than have a series-shunt voltage divider configuration to model the sensor impedance, we use two parallel branches instead.

Photo Detector / Transimpedance Amplifier Circuit

An example of a current based sensor is a photo detector diode. We can model this type of detector as a current source with a parallel capacitor as shown in the following photo detector / transimpedance amplifier circuit, borrowed from the Microchip datasheet for their MCP6021 device:

photo-diode-transimpedance-amplifier

This transimpedance circuit converts the input current Ii into output voltage Vo.

Here’s how we can model this in SCE. We split the circuit into two stages: a current based sensor stage, and an inverting amplifier stage. Below we show the definition for the sensor stage:

2016-10-23-2

Though the current based sensor stage allows for a series R-L branch, we aren’t using one here.

A note on how the R, L, C parameters work (they work similarly in the other sensor stages): Left unchecked, the resistor is treated as being a “short” having zero resistance. An unchecked inductor is also treated as a “short’ having zero inductance. If both resistor and inductor are left unchecked, SCE interprets this configuration to mean the whole R-L branch should be “open” — that is, it’s not there at all.

We do keep the capacitor shunt, though, and we’ve given it a value of 100 pF as per the Microchip circuit. If we hadn’t checked the capacitor field, the capacitor branch would be treated as “open” as well, and we’d end up with a naked current source having an infinite output impedance. In such cases, SCE automatically and implicitly adds 1 PetaOhm of parallel resistance to model this “infinite” impedance.

We’ve arbitrarily set the input signal current to 1 uA. As before, this signal amplitude is used for all frequencies in the simulation.

Below is the definition of the amplifier stage as implemented in SCE. We use a “generic” inverter stage — generic in that it allows us to use arbitrary passive networks for the input, feedback, and ground path impedances. Here, the input and ground path impedances are defined shorts, as per the circuit above, and the feedback path is a parallel RC, which is defined by popping up the dialog as shown on the right. We’ve also used the built-in op-amp database of SCE and selected the MCP6021 amplifier model:

photo-diode-transimpedance-amplifier-iv

Here is the bode chart for the sensor-plus-transimpedance amplifier circuit. Note the “gain” defined here is not a ratio of output to input voltages, but rather, is the transimpedance — the ratio of output voltage to input current.

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Due to careful selection of parameter values, we have a nice flat response out to 200 kHz, with no evidence of peaking.

Charge based sensors

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The charged based sensor stage of SCE is similar in construction to the current based sensor stage, but uses a charge source rather than a current source. (Remember, current is the time derivative of charge, or vice versa, charge is the time integral of current.)

A piezo-electric sensor

A good example of a charge based sensor is a piezo-electric sensor. These sensors, either made of solid quartz or similar, or of manufactured ceramics, produce electrical charges when the sensor is squeezed, twisted, pressed, or otherwise distorted mechanically. Such sensors are quite versatile, and can be used as force or strain sensors, pressure sensors, accelerometers, and as acoustic pickups and percussion triggers. Quartz piezo-electrics can work at very high temperatures, making them ideal in many industrial/aerospace applications.

For our example here, we’ll be modeling a ceramic sensor — the Murata 7BB-35-3L0, which is a disk sensor as pictured below.

2016-10-23-4

This sensor can be used as an acoustic pickup — or in the cases we’ve used it for, as a “percussion trigger” in an electronic midi drum kit.

There are various ways to model piezos. A simple method is to model it as a charge source in parallel with a capacitance, and you will see this quite often in the literature. We’ll also add a parallel resistance, which represents the “leakage” resistance in the sensor that determines the sensor’s output resistance at DC:

piezo-sensor-iv

NOTE: This simple model does not capture any resonances in the piezo, but note that piezos do in fact resonate, and may have more than one resonant frequency. We’ll be showing a better model for piezos in later articles, but for now, just assume the sensor is being used in the flat region of its response, away from any peaking. This is a common thing to do in practice, but also note that in practice, not remembering that there is resonance may very well trip you up.

The Murata 7BB-35-3LO sensor has 30 nF of capacitance according to its datasheet. No DC resistance is given, but we’ll estimate, say, 20 MOhms. Most of these sensors have very high resistance values in the 10s to 100s of MOhms, and even GOhms and beyond. The Murata datasheet also shows a resonant frequency of 3 kHz that we’ll be ignoring for this blog post.

We define the piezo stage as follows in SCE:

2016-10-24

We leave the inductance unchecked, so it’s treated as a short.

NOTE: You’ll notice that there is no check box for the capacitor. This field is not optional. The reason for this is that SCE works by primarily using signal voltages as it goes from stage to stage. It cannot work directly with charges. What actually happens behind the scenes is that SCE converts the charge source and parallel capacitor into it a voltage source and series capacitor, reminiscent of a Norton to Thevenin  conversion:

norton-to-thev-charge-source

Having measured sensors like the 7BB-35 in the lab, we know that they can output 100s of mV quite easily by tapping on the sensor through a chunk of sanding block foam (to protect the sensor). To get an output voltage in this range, we’ll set the output charge to 10nC. How does this relate to 100s of mV? By the following equation, which uses the charge/voltage equation for capacitors:

\(\displaystyle \frac{q}{{{{C}_{p}}}}=\frac{{10\,nC}}{{30\,nF}}=333\,mV\)

NOTE: As usual with the sensor stages of SCE, we are going to pretend that the sensor outputs the same signal amplitude at all frequencies we might happen to sweep during simulation.

Because of the capacitance in the sensor and its relatively small output charge, using a piezo sensor in a circuit can be tricky, as cable capacitances and inductances can easily upset the measurements. This can be handled by using a “charge amplifier”, which mitigates the effects of such parasitics. An example of such a circuit is given below:

charge-mode-amplifier-ii

Here, we’re modeling a cable capacitance of 300 pF and then using an inverting amplifier stage with parallel RC feedback.

NOTE: SCE has a more sophisticated way to handle cable parasitics through its interconnect modeling. For sake of simplicity in this blog post, we’ll just directly model the cable as a capacitive shunt and leave the interconnect parasitics of SCE turned off.

The op-amp chosen is a Texas Instrument TLV2771, which we select from the built-in op-amp database.

We model the charge amplifier and how the signal chain in SCE as follows. We also show the Parallel RC popup dialog used for the amplifier feedback definition:

charge-amplifier-signal-chain

Next, let’s take a peek at the bode chart for this signal chain. As was the case with current based sensor stages, the bode charts for charge based sensors are actually transimpedance plots, in this case relating output voltage Vo to input charge q:

2016-10-24-5

Charge amplifiers are cool because the maximum transimpedance gain (and thus the maximum output voltage) that occurs in the flat region of the response is directly controlled by the feedback capacitor Cf, and you can quite easily compute this voltage as follows, where our Cf is 80 nF:

\(\displaystyle Max\,voltage=\frac{q}{{{{C}_{f}}}}=\frac{{10\,nC}}{{80\,nF}}=125\,mV\)

Note from this formula that the only thing that matters, as far as the maximum output is concerned, is that you know the input charge and the feedback capacitor. Any nasty cable parasitics do not affect the result. That’s the major advantage of using charge amplifiers. In effect, you set the transimpedance gain solely by the value of the feedback capacitor. It should be pointed out, though, that this only holds in the flat region of the response — and you still need to worry about the frequency response in general. Don’t get complacent!

There’s plenty more we could discuss on the use of such charge amplifiers, but we’ll leave that for another day.

Conclusion

We’ve just scratched the surface on modeling sensors in SCE, and we’ve just scratched the surface in regards to the various complexities of using the sensors mentioned in this article. We hope to have more detailed discussions of these topics in future articles.

New pre-release of Signal Chain Explorer V 0.968

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This update adds the ability to specify other waveforms for HFI and EFI gargoyles (aka interferers) besides the default sine waves. You can now specify square waves, trapezoid waves, rectified sines, impulses, etc. This new specification is not fully implemented in that we still only compute the gargoyles at their primary frequencies (ie. 1 / period of wave). Someday we’ll take the shape of the wave and compute the interference at harmonic frequencies as well. But that day is not today.

Instead, we have the following … er … “baby step”: A new field has been added for each gargoyle where you specify the maximum slew rate for that gargoyle. Before, the slew rates were auto-calculated based on assuming the waveforms were sine waves at the given frequencies. This latest change makes our interference calculations a bit more sophisticated in that the slew rates are independent of the primary frequencies.

Along with this change, we’ve added a new high level dialog box (under the main Utilities menu) that helps you compute reasonable slew rates, given the amplitude and frequency of your gargoyles.

Anyway, check out the new version on the downloads page.